1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to new device configurations and manufacturing method for a metal oxide semiconductor field effect transistor (MOSFET) device with planar split gate structure to improve device performance.
2. Description of the Prior Art
Even though a semiconductor power device with planar gate structure is more compatible with multiple foundries and can be produced at a lower production cost, however, conventional technologies for manufacturing a metal oxide semiconductor field effect transistor (MOSFET) device with planar gates are still challenged by several technical difficulties and limitations. Specifically, the DMOS process produces a channel with uneven channel doping density as shown in FIG. 1D such that precision control of threshold is difficult and the device is susceptible to punch-through. As shown in FIG. 1D, the channel has a peak doping level near the source region that determines the threshold. The doping level drops sharply as the channel extends into the drift region. This channel dopant profile has some problems. First, the extent of source and body diffusion affects the peak channel doping level therefore precision control of gate threshold is difficult since that would require highly precision control of source and body diffusion. Second, the sharp decrease of doping level as the channel extends into the drift region causes dramatically reduction of the charge level in this region therefore the device is vulnerable to punch-through. Furthermore, a MOSFET device that requires a reduced capacitance for high frequency applications is still limited by a high capacitance (Cgd) at low bias due to the overlap of the planar gate over the drain region. Specifically a higher Cgd occurs due to a capacitive coupling between the planar gates and the drain across an epitaxial layer not covered with the body regions, i.e., the coupling of the planar gates to the drain across the epitaxial layer between the body regions.
A semiconductor power device usually comprises a plurality of power transistor cells in parallel. Referring to FIG. 1A for a single cell of a typical conventional vertical DMOS field effect transistor (FET) device configured with a planar structure having horizontal channel and gate, the channel is diffused from the edge of the source region near the gate. A JFET implant, e.g., a N-type dopant implant for a NMOSFET device, may be used to reduce the increase of the on-resistance caused by the lateral diffusion that pinches the drain regions between the channel regions. However, as discussed above, such device has limited high frequency applications at a low bias due to the high gate-to-drain capacitance caused by the coupling of the planar gates to drain across the epitaxial and drift regions between the body regions.
Furthermore, a DMOS device with planar gate is limited by several technical limitations that the cell pitch cannot be easily reduced. Specifically, in reducing a cell pitch of a DMOS device, a large distance between the body regions leads to a reduced breakdown voltage. On the other hand, a small distance between the body regions causes a high drain to source on-resistance Rdson. Baliga disclosed in U.S. Pat. No. 6,800,897 (issued on Oct. 5, 2005) and U.S. Pat. No. 6,791,143 (issued on Sep. 14, 2004) a SSCFET device as that shown in FIG. 1B wherein the device disclosed in the U.S. Pat. No. 6,791,143 is named as a SSCFET in a November 2003 publication where SSC stands for Silicon Semiconductor Corporation. For a n-channel MOSFET device, the SSCFET structure is implemented with retrograde N-type JFET implant region to improve device on resistance. The JFET implant region is further combined with a buried P-region to shield the gate from directly coupling to the drain as that often occurs in a conventional DMOS device. However, the SSCFET structure as shown in FIG. 1B does not provide an effective resolution to these technical difficulties due to the competing design requirements. Specifically, a high dose JFET implant for the purpose of achieving a lower resistance also compensates the P-body and the P-shield implant regions. For these reasons, the demands for high performance power device with high efficiency that is suitable for high frequency applications cannot be satisfied by the semiconductor power devices with planar gates as produced now by the conventional technologies.
In U.S. Pat. No. 6,639,276, entitled “Power MOSFET with ultra-deep base and reduced on resistance” (issued on Oct. 28, 2003), a MOSFET device is disclosed as that shown in FIG. 1C wherein the MOSFET includes a highly doped semiconductor substrate 30 to support a lightly doped epitaxial layer 31. The MOSFET device further includes highly doped source regions 33 of the same conductivity as the epitaxial layer 31 formed in respective lightly doped body regions 32 of an opposite conductivity type. The MOSFET device also includes gate insulation layers 34 formed over invertible channels 32′. The gate insulation layers 34 do not extend over the entire area of common conduction regions 35, which are located between the body regions 32. The gate insulation layers only extend over a portion of the common conduction regions 35. The insulation spacer 50 is disposed between the gate electrodes 51 and covers the remaining portions of the common conduction regions 35. The insulation spacers 50 make contact with the top surface of the epitaxial layer 31 and cover a substantial portion of each common conduction region 35. A source contact 39, which may be made from aluminum, is provided to make contact with the source regions 33 and body regions 32. Insulating sidewalls 38 and insulating top layers 37 are interposed between the gate electrodes 51 and the source contact 39 in order to insulate the two from one another. The insulating spacers 50 are drastically thickened and preferably expand over a substantial portion of the width of common conduction regions 35. The insulating spacers 50 reduce the area of the gate electrodes 51 overlying the surface of common conduction regions 35. This results in a reduced gate to drain capacitance. The MOSFET further includes deep implanted junctions 92 formed in the body of the epitaxial layer 31. The concentration of dopants in deep implanted junctions 92 may be increased. An increase in the dopant concentration of deep implanted junctions 92 allows for an increase in the dopant concentration of the common conduction region 35, which improves Rdson without sacrificing the breakdown voltage. The device shown in FIG. 1C has an improved structure over the devices as shown in FIGS. 1A and 1B. It applies a split gate configuration to reduce the gate to drain capacitance without sacrificing other performance requirements. But similar to the devices as shown in FIGS. 1A and 1B, this device is also a DMOS device that the channel 32′ is formed by double diffusion process of source region 33 and body region 32. All DMOS devices share the common channel doping profile as shown in FIG. 1D. As discussed above, the device as shown in FIG. 1C has a threshold voltage that is difficult to control and a channel that is vulnerable to punch-through.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices with planar gate such that the above discussed problems and limitations can be resolved. For those of ordinary skill the art, a planar gate MOSFET device compatible with multiple foundries is desirable for reducing production cost. It is further desirable that such devices have low capacitance at low and high bias and also has low on-resistance times a gate charge product. It is further desirable that such device being more resistant to punch-through and have a precisely controlled stable threshold voltage.